ds106-1 (v1.7) october 18, 2004 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. introduction the xilinx automotive (xa) spartan?-iie 1.8v field-pro- grammable gate array family is specifically designed to meet the needs of high-volume, cost-sensitive automotive electronic applications. the family gives users high perfor- mance, abundant logic resources, and a rich feature set, all at an exceptionally low price. the five-member family offers densities ranging from 50,000 to 300,000 system gates, as shown in ta b l e 1 . system performance is supported beyond 200 mhz. spartan-iie devices deliver more gates, i/os, and features per dollar than other fpgas by combining advanced pro- cess technology with a streamlined architecture based on the proven virtex?-e platform. features include block ram (to 64k bits), distributed ram (to 98,304 bits), 19 selectable i/o standards, and four dlls (delay-locked loops). fast, predictable interconnect means that succes- sive design iterations continue to meet timing requirements. xa devices are available in both the extended-temperature q-grade (-40 c to +125 c) and industrial i-grade (-40 c to +100 c) and are qualified to the industry-recognized aec-q100 standard. the xa spartan-iie family is a superior alternative to mask-programmed asics. the fpga avoids the initial cost, lengthy development cycles, and inherent risk of con- ventional asics. also, fpga programmability permits design upgrades in the field with no hardware replacement necessary (impossible with asics). features aec-q100 device qualification and full ppap support available in both extended temperature q-grade and i-grade guaranteed to meet full electrical specifications over t j = ?40c to +125c second generation asic replacement technology - densities as high as 6,912 logic cells with up to 300,000 system gates - very low cost system-level features - selectram+? hierarchical memory: 16 bits/lut distributed ram configurable 4k-bit true dual-port block ram fast interfaces to external ram - dedicated carry logic for high-speed arithmetic - efficient multiplier support - cascade chain for wide-input functions - abundant registers/latches with enable, set, reset - four dedicated dlls for advanced clock control eliminate clock distribution delay multiply, divide, or phase shift - four primary low-skew global clock distribution nets - ieee 1149.1 compatible boundary scan logic versatile i/o and packaging - low-cost packages available in all densities - 19 high-performance interface standards lvttl, lvcmos, hstl, sstl, agp, ctt, gtl lvds and lvpecl differential i/o - up to 120 differential i/o pairs that can be input, output, or bidirectional fully supported by powerful xilinx ise development system - fully automatic mapping, placement, and routing - integrated with design entry and verification tools - extensive ip library including dsp functions 0 spartan-iie 1.8v fpga automotive xa product family: introduction and ordering ds106-1 (v1.7) october 18, 2004 00 preliminary product specification r table 1: xa spartan-iie fpga family members device logic cells typical system gate range (logic and ram) clb array (r x c) total clbs maximum available user i/o (1) maximum differential i/o pairs distributed ram bits block ram bits xa2s50e 1,728 23,000 - 50,000 16 x 24 384 102 83 24,576 32k xa2s100e 2,700 37,000 - 100,000 20 x 30 600 102 86 38,400 40k xa2s150e 3,888 52,000 - 150,000 24 x 36 864 182 114 55,296 48k xa2s200e 5,292 71,000 - 200,000 28 x 42 1,176 182 120 75,264 56k xa2s300e 6,912 93,000 - 300,000 32 x 48 1,536 182 120 98,304 64k notes: 1. user i/o counts include the four global clock/user input pins. see details in table 3, page 5
spartan-iie 1.8v fpga automotive xa product family: introduction and ordering infor9/20/2003ation 2 www.xilinx.com ds106-1 (v1.7) october 18, 2004 1-800-255-7778 preliminary product specification r general overview the spartan-iie family of fpgas have a regular, flexible, programmable architecture of configurable logic blocks (clbs), surrounded by a perimeter of programmable input/output blocks (iobs). there are four delay-locked loops (dlls), one at each corner of the die. two columns of block ram lie on opposite sides of the die, between the clbs and the iob columns. the xc2s400e has four col- umns of block ram. these functional elements are inter- connected by a powerful hierarchy of versatile routing channels (see figure 1 ). spartan-iie fpgas are customized by loading configura- tion data into internal static memory cells. unlimited repro- gramming cycles are possible with this approach. stored values in these cells determine logic functions and intercon- nections implemented in the fpga. configuration data can be read from an external serial prom (master serial mode), or written into the fpga in slave serial, slave parallel, or boundary scan modes. spartan-iie fpgas are typically used in high-volume appli- cations where the versatility of a fast programmable solu- tion adds benefits. spartan-iie fpgas are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. spartan-iie fpgas achieve high-performance, low-cost operation through advanced architecture and semiconduc- tor technology. spartan-iie devices provide system clock rates beyond 200 mhz. spartan-iie fpgas offer the most cost-effective solution while maintaining leading edge per- formance. in addition to the conventional benefits of high-volume programmable logic solutions, spartan-iie fpgas also offer on-chip synchronous single-port and dual-port ram (block and distributed form), dll clock driv- ers, programmable set and reset on all flip-flops, fast carry logic, and many other features. spartan-iie family compared to spartan-ii family higher density and more i/o higher performance unique pinouts in cost-effective packages differential signaling - lv d s, b u s lv d s, lv p e c l v ccint = 1.8v - lower power - 5v tolerance with external resistor - 3v tolerance directly lvttl and lvcmos2 input buffers powered by v cco instead of v ccint unique larger bitstream
spartan-iie 1.8v fpga automotive xa product family: introduction and ordering infor9/20/2003ation ds106-1 (v1.7) october 18, 2004 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r dc specifications absolute maximum ratings (1) figure 1: basic spartan-iie family fpga block diagram dll dll dll dll b l oc k ra m b l oc k ra m b l oc k ra m b l oc k ra m i/ o l og i c ds077 _ 01 _ 05210 2 symbol description min max units v ccint supply voltage relative to gnd ?0.5 2.0 v v cco supply voltage relative to gnd ?0.5 4.0 v v ref input reference voltage ?0.5 4.0 v v in input voltage relative to gnd (2,3) ?0.5 4.05 v v ts voltage applied to 3-state output (3) ?0.5 4.0 v t stg storage temperature (ambient) ?65 +150 c t j junction temperature - +135 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. 2. v in should not exceed v cco by more than 3.6v over extended periods of time (e.g., longer than a day). 3. maximum dc overshoot must be limited to either v cco + 0.5v or 10 ma, and undershoot must be limited to ?0.5v or 10 ma, whichever is easier to achieve. the maximum ac conditions are as follows: the device pins may undershoot to ?2.0v or overshoot to v cco + 2.0v, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 ma. 4. for soldering guidelines, see the packaging information on the xilinx web site.
spartan-iie 1.8v fpga automotive xa product family: introduction and ordering infor9/20/2003ation 4 www.xilinx.com ds106-1 (v1.7) october 18, 2004 1-800-255-7778 preliminary product specification r recommended operating conditions dc characteristics over operating conditions spartan-iie product availability ta b l e 2 shows the package and speed grades available for spartan-iie family devices. ta bl e 3 shows the maximum user i/os available on the device and the number of user i/os available for each device/package combination. symbol description min max units t j junction temperature ?40 125 c v ccint supply voltage relative to gnd (1) 1.8 ? 5% 1.8 + 5% v v cco supply voltage relative to gnd (2) 1.2 3.6 v t in input signal transition time (3) -250ns notes: 1. functional operation is guaranteed down to a minimum v ccint of 1.62v (nominal v ccint ?10%). for every 50 mv reduction in v ccint below 1.71v (nominal v ccint ?5%), all delay parameters increase by 3%. 2. minimum and maximum values for v cco vary according to the i/o standard selected. 3. input and output measurement threshold is ~50% of v cco . symbol description min max units i ccintq quiescent v ccint supply current (1) xa2s50e - 200 ma xa2s100e - 350 ma xa2s150e - 450 ma xa2s200e - 550 ma xa2s300e - 650 ma notes: 1. with no output current loads, no active pull-up resistors, and all i/o pins 3-stated and floating. table 2: spartan-iie package and speed grade availability device pins 144 256 type plastic tqfp fine pitch bga code tq144 ft256 xa2s50e -6 i,q xa2s100e -6 i,q xa2s150e -6 - i,q xa2s200e -6 - i,q xa2s300e -6 - i,q notes: 1. q = ?40 c to +125 c (t j ) 2. i = ?40 c to +100 c (t j )
spartan-iie 1.8v fpga automotive xa product family: introduction and ordering infor9/20/2003ation ds106-1 (v1.7) october 18, 2004 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r ordering information table 3: spartan-iie user i/o chart device maximum user i/o available user i/o according to package type tq144 ft256 xa2s50e 102 102 - xa2s100e 102 102 - xa2s150e 182 - 182 xa2s200e 182 - 182 xa2s300e 182 - 182 xa2s50e -6 tq 144 q example: temperature range number of pins package type device type speed grade device ordering options device speed grade package type / number of pins temperature range (t j ) xa2s50e -6 standard performance tq144 144-pin plastic thin qfp q = automotive extended ?40c to +125c xa2s100e ft256 256-ball fine pitch bga i = automotive industrial ?40c to +100c xa2s150e xa2s200e xa2s300e
spartan-iie 1.8v fpga automotive xa product family: introduction and ordering infor9/20/2003ation 6 www.xilinx.com ds106-1 (v1.7) october 18, 2004 1-800-255-7778 preliminary product specification r revision history version no. date description 1.0 07/17/02 initial xilinx release. 1.1 11/18/02 added xc2s400-e and xc2s600-e devices. added fg676 to package list. 1.2 11/26/02 updated max user i/o and differential i/o pairs in ta b l e 1 and max user i/o in ta b l e 3 . updated notes for recommended operating conditions. 1.3 06/04/03 changed five-member family to seven-member family in first paragraph. 1.4 06/16/03 updated features list. added dc characteristics over operating conditions table. deleted ?fg676? from ta bl e 2 , ta b l e 3 , and the device ordering options section. 1.5 07/16/03 updated features list, ta b l e 1 , dc characteristics over operating conditions table, and ta bl e 3 . 1.6 09/24/03 updated title to read "product specification" (removed "advance") 1.7 10/18/04 extensive edits to update family from iq to xa
|
